Integrated circuit (IC) memory devices allow large amounts of data to be stored in relatively small physical packages. One such device is a random access memory (RAM). A RAM comprises a plurality of memory cells which are typically arranged in a matrix of rows and columns. Separate bits of data may be written into, stored, and read out of each of these memory cells. For this, each memory cell is accessible by at least one row line commonly referred to as a "word line."
According to previously developed techniques, a hierarchical scheme can be used for word line addressing or decoding. More specifically, a global word line may be used in conjunction with a plurality of local word lines for access into one or more particular memory cells. Such a previously developed hierarchical scheme is supported by, at a minimum, a global word line driver, one or more local word line drivers, and a phase driver. Typically, the phase driver is coupled to the local word line drivers by at least two separate connecting or metal lines. Each local word line driver is implemented using three or more transistor devices.
An on-going challenge in the design of IC memories is to reduce the size of a surface layout for a memory device. Accordingly, it would be desirable to reduce the surface layout required to implement a hierarchical row decode scheme.